Interfacing low power level, high speed digital-type switching circuitry with high current capability devices has previously required a compromise of several desired circuit parameters including switching speed, noise suppression, operating frequency range, power dissipation and circuit complexity. The increasingly diverse application of low power level logic circuitry to relatively high current analog circuit applications mandates careful consideration of interface circuitry capabilities since the interface circuitry often establishes the limiting parameters in digital controlled analog operations, diminishing the value of such control systems. The circuitry of the present invention provides low power, high speed switching capability over a wide frequency range using relatively few circuit components. This inventive circuitry utilizes a hybrid network of complementary-symmetry arranged bipolar and unipolar transistors to control the high current switching of vertical metal oxide semiconductor transistors, hereinafter referred to as VMOS transistors. The circuitry of the present invention provides efficient high current switching capability controlled by relatively low power level logic type devices.
Many applications of such interface circuitry further require isolation or inhibiting means to prevent false triggering of the circuit switching devices. For purposes of the present invention, false triggering is generally caused by fluctuations in circuit reference potentials. The circuitry of the present invention utilizes a novel structure for floating the circuit reference potential, that is, allowing the reference potential to vary at, above, or below ground potential in a manner to substantially follow an output reference potential, compensating the switching devices for output voltage fluctuations. The effects of input signal transients are suppressed by a plurality of complementary-symmetry arranged metal oxide semiconductor field effect transistors having threshold switching voltages approximately equal to about one-half of an anticipated signal input.